cy27020 spread spectrum clock generator cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-07273 rev. *h revised november 2, 2016 spread spectrum clock generator features supports clock requirements for printers 48-mhz spread spectrum clock output 48-mhz reference clock output two selectable spread percentages: ?1% and ?3% integrated loop filter 48-mhz crystal or external clock input 3.3-v supply operation (2.5-v functional) 8-pin small outline integrated circuit (soic) package functional description the cy27020 clock generator provides a low emi clock output for printers. it features spread spectrum technology, a modulation technique designed specifically for reducing emi at the fundamental frequency and its harmonics. for a complete list of related documentation, click here . frequency table xin sson# sssel refout clkout 48.00 mhz 0 0 48.00 mhz 48.00 mhz at ?1% 48.00 mhz 0 1 48.00 mhz 48.00 mhz at ?3% 48.00 mhz 1 0 48.00 mhz 48.00 mhz (no spread) 48.00 mhz 1 1 48.00 mhz 48.00 mhz (no spread) xin xout oscillator pll sscg sson# sssel refout clkout logic block diagram
cy27020 document number: 38-07273 rev. *h page 2 of 9 spread spectrum clock generation (sscg) spread spectrum clock generation (sscg) is a frequency modulation technique used to reduce electromagnetic interference radiation generated by repetitive digital signals, mainly clocks. a clock accumulates electromagnetic energy at its center frequency and its harmonics. spread spectrum distributes this energy over a small frequency band and decreases the peak value of radiated energy over the spectrum. this technique is achieved by modulating the clock around or below the center of its nominal frequency by a certain percentage (which also determines the energy distribution band). the sscg function is enabled when sson# pin is asserted low, resulting in a spread bandwidth that is down spread by either ?1% or ?3%, selected by sssel (see table on page 1 ). figure 2. no spread vs down spread example pin configuration figure 1. 8-pin soic pinout 1 2 3 4 8 7 6 5 sson# refout sssel xout clkout vdd vss xin cy27020 pin description pin name i/o type [1] description 1clkouto fixed frequency 48.00 mhz spread spectrum clock output. see table on page 1 for frequency selections 2 vdd pwr 3.3-v power supply 3 vss pwr ground 4xin i oscillator buffer input. connect to an external parallel resonant crystal (nominally 48.00 mhz) or externally generated 48 mhz reference clock. 5xouto oscillator buffer output. connect to an external parallel resonant crystal. do not connect when an externally generated reference clock is applied at xin. 6 sssel i pu spread spectrum percentage select input. see table on page 1 for details. 7 refout o ? buffered output of xin. 8 sson# i pd spread spectrum enable input. when asserted low, spread spectrum is enabled. note 1. pu = internal pull-up resistor, pd = internal pull-down resistor.
cy27020 document number: 38-07273 rev. *h page 3 of 9 absolute maximum conditions exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. [2] minimum input voltage relative to v ss : ...............v ss ? 0.3 v maximum input volta ge relative to v dd : ............. v dd + 0.3 v storage temperature: ................................. ?65 c to 150 c operating temperature: .................................. 0 c to 70 c maximum electrostatic discharge (esd) protection: ...... 2 kv maximum power supply: ............................................... 5.5 v operating voltage: ..............................................2.5 v?3.6 v this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, care should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, the i/o pins should be constrained to the range: v ss < i/o < v dd unused inputs must always be tied to an appropriate logic voltage level (either v ss or v dd ). dc electrical specifications (v dd = 3.3 v 10%, t a = 0 c to 70 c) [3] parameter description conditions min typ max unit v il input low voltage sson#, sssel ? ? 0.8 v v ih input high voltage 2.2 ? ? v v thxin xin threshold voltage 0.3 v dd 0.5 v dd 0.7 v dd v i il1 input low current sson# = v ss ?5 0 5 ? a i ih1 input high current sson# = v dd 3820 ? a i il2 input low current ssel = v ss ?36 ?16.5 ?7.4 ? a i ih2 input high current ssel = v dd ?5 0 5 ? a i dd3.3v dynamic supply current no output load ? 20 25 ma v ol output low voltage i ol = 4.0 ma ? ? 0.4 v v oh output high voltage i oh = ?4.0 ma 2.4 ? ? v cin input capacitance pins 6 and 8 ? 3 5 pf cx xin, xout capacitance pins 4 and 5 ? 3 5 pf pu/pd pull-up/pull-down resi stance sson#, sssel 100 200 400 k ? notes 2. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required. 3. in applications where a crystal is used for the input reference clock, refer to the crystal manufacturer?s specifications for the required crystal load capacitor value.
cy27020 document number: 38-07273 rev. *h page 4 of 9 ac electrical specifications (v dd = 3.3 v 10%, t a = 0 c to 70 c) parameter description conditions min typ max unit ifr input frequency range 44 48 52 mhz t r rise time [4, 5] ?12ns t f fall time [4, 5] ?12ns ss% spread spectrum percentage sson# = 0, sssel = 0 ? ?1 ? % sson# = 0, sssel = 1 ? ?3 ? % t pu power-up to stable output [6] all output clocks ? ? 3 ms t dc clock duty cycle [4, 6] cl = 15 pf 45 50 55 % t ccj refout cycle-to-cycle jitter [4, 6] cl = 15 pf ? ? 350 ps clkout cycle-to-cycle jitter [4, 6] ? 100 250 ps application sche matic example figure 3. application schematic example [7, 8] x in xout c l 2 c l1 0.1uf 33 33 v d d refout clkout cy27020 1 7 5 4 sssel s s o n # 8 6 vss 3 2 vss vss 48 mhz vdd notes 4. parameters are guaranteed by design and characterization. not 100% tested in production. all parameters specified with fully loaded outputs. all outputs loaded with 15 pf. 5. measured between 0.1 x v dd and 0.9 x v dd volts. 6. triggering is done at 1.5 v. 7. the circuit shows -1.0% spread. refer to frequency table on page 1 for details. 8. use the crystal manufacturer?s recommended values for cl1 and cl2 load capacitors.
cy27020 document number: 38-07273 rev. *h page 5 of 9 ordering code definitions ordering information part number package type production flow pb-free CY27020SXC 8-pin soic commercial, 0 c to 70 c CY27020SXCt 8-pin soic - tape and reel commercial, 0 c to 70 c x = blank or t blank = tube; t = tape and reel temperature range: c = commercial = 0 ? c to +70 ? c x = pb-free; x absent = leaded package type: s = 8-pin soic base part number company id: cy = cypress cy 27020 s x c x
cy27020 document number: 38-07273 rev. *h page 6 of 9 package drawing and dimension figure 4. 8-pin soic (150 mils) s0 815/sz815/sw815 packa ge outline, 51-85066 51-85066 *h
cy27020 document number: 38-07273 rev. *h page 7 of 9 acronyms document conventions units of measure table 1. acronyms used in this document acronym description clkout reference clock out emi electromagnetic interference esd electrostatic discharge pd power down pll phase locked loop ppm parts per million ss spread spectrum ssc spread spectrum clock sscg spread spectrum clock generation sson spread spectrum on table 2. units of measure symbol unit of measure c degree celsius k ? kilohm mhz megahertz a microampere s microsecond ma milliampere ms millisecond mw milliwatt ns nanosecond ? ohm pf picofarad ps picosecond vvolt wwatt
cy27020 document number: 38-07273 rev. *h page 8 of 9 document history page document title: cy27020, spread spectrum clock generator document number: 38-07273 rev. ecn no. submission date orig. of change description of change ** 110661 02/19/02 xht new data sheet. *a 122868 12/21/02 rbi add power up requirements to maximum rating information *b 279429 see ecn rgl added lead-free devices *c 2759365 09/02/2009 tsai updated template. post to external web. *d 2899304 03/25/2010 cxq removed inactive parts from ordering information updated package drawing and dimension . *e 3041840 09/29/2010 cxq removed ?ic? from end of document title. fixed various formatting and typographical errors. change all sson pin references to sson#. added row to table 1 for explicit select pin functional explanation. removed references to cera-lock input. removed redundant note 3. *f 4162220 10/16/2013 cinm updated package drawing and dimension : spec 51-85066 ? changed revision from *d to *f. updated in new template. completing sunset review. *g 4587350 12/05/2014 aju added related documentation hyperlink in page 1. *h 5507104 11/02/2016 pawk updated the template.
document number: 38-07273 rev. *h revised november 2, 2016 page 9 of 9 cy27020 ? cypress semiconductor corporation, 2002-2016. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informat ion or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly desi gn, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear inst allations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury , death, or property damage ("unintended uses"). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all uninte nded uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community forums | projects | video | blogs | training | components technical support cypress.com/support
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